1. Field of Invention
The present invention generally relates to memory device, and more particularly to a bit line precharge circuit in the memory device.
2. Description of Prior Art
Flash memory components are experiencing a trend toward progressive miniaturization, which has currently reached the lower submicron range (0.25 μm, 0.18. μm, 0.13. μm) for the characteristic feature sizes. However, the decreasing feature sizes conflict with the requirements of a reduced supply voltage and the reduced power consumption, and with the trend toward ever higher system clock frequencies. The most significant part of a nonvolatile memory component in such a respect is the sense amplifier, because it is very important to maintain a high read access speed and a low current consumption while, at the same time, the stability of the sense amplifier remains high.
In the sense amplifiers used to date, it has been necessary to make a compromise between current consumption and access time. A short access time is normally associated with a high current consumption, and vice-versa. Some applications require a very low current consumption, and, to achieve such an aim, read access has been divided into two phases (precharging and sensing).
In order to complete a read operation of a flash memory, the selected bit lines must be charged to a designed voltage level before sensing starts. Therefore, if the selected bit lines are quick and accurate settled to the target level, thus sensing can be advanced.
Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional bit line precharge circuit 10. As shown in FIG. 1, the bit line precharge circuit 10 is composed of a plurality of precharge sub-circuits PC[1]˜PC[n]. The precharge sub-circuit PC[i] (i.e. i is an integer from 1 to n) comprises a controllable current-voltage converter L[i], a sensed amplifier Amp[i], a memory cell Cell[i], and a drain bias controller DBC[i]. The connection of the controllable current-voltage converter L[i], the sensed amplifier Amp[i], and the drain bias controller DBC[i] is shown in FIG. 1 without describing herein.
The drain bias controller DBC[i] is coupled to a memory cell Cell[i]. The memory cell Cell[i] has a NMOS transistor N3 and an effective capacitance CBL of a bit line BL[i]. The controllable current-voltage converter L[i] comprises a NMOS transistor N1 and two PMOS transistor P1, P2, and the connection of the transistors N1, P1, and P2 is shown in FIG. 1 without describing herein.
It is noted that the drain bias controller DBC[i] comprises an inverter Inv and a clamping NMOS transistor N2, and the inverter Inv and the clamping NMOS transistor N2 form a negative feedback loop to control the drain bias of the clamping NMOS transistor N2. By using the negative feedback loop, the bit line BL[i] can be fast precharged to the target level, and the voltage level of the bit line BL[i] is stable without large fluctuation.
Accordingly, the conventional bit line precharge circuit stated above uses an inverter and a clamping NMOS transistor with feedback loop acting as a drain bias controller, and it provides a fast and stable bit line precharging according to the concept of negative feedback. However, as a large number of bits reading at a time, it will consume large layout area and power. For example, a page mode read function needs reading 128 bits at the same time, and thus the total 128 precharge sub-circuits (i.e. n=128 in FIG. 1) are included and are enabled.
Referring to U.S. Pat. No. 7,082,069 invented by Chou et al., Chou et al. provide a fast bit line precharge circuit without a plurality of drain bias controllers. However, it needs an extra column of memory cells as a dummy bit line and a level detector to predict the precharging is successful in current selected bit lines, but usually it is not easy to design a balanced loading on reference path and cell path, and has layout area expansion due to a extra dummy bit line and its Well to Well layout rule.
In summary, one of the conventional bit line precharge circuits may have the large area and the large power consumption, and another one of the conventional bit line precharge circuits may have the extra dummy bit line which causes the layout area expansion.